Parallel Redundant Single-Electron Device and Method of Manufacture

ABSTRACT

A method of manufacturing a parallel redundant array of single-electron devices. The method includes (a) providing a mask for diffusing a plurality of n-doped regions defined by a first set of a plurality of active regions, (b) providing a mask for disposing a plurality of polysilicon gates defined by a second set of a plurality of exposed regions, wherein an offset between a first member of the plurality of the exposed region of the first set differs in offset from a second member of the plurality of the exposed region of the second set, and (c) fabricating the parallel redundant array of single-electron devices as a function of the offset.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based on and claims the benefit of U.S. ProvisionalApplication Ser. No. 60/823,787 filed on Aug. 29, 2006, entitled“Self-Synchronization of Oscillators with Single-Electron Restoration,”commonly assigned with this application and incorporated herein byreference in its entirety, and are related to application Ser. No.______, Docket No. TI-63240, entitled “Single-ElectronInjection/Extraction Device for a Resonant Tank Circuit and Method ofOperation Thereof” and is also related to application Ser. No. ______,Docket No. TI-63241, entitled “Single-Electron Tunnel Junction for aComplementary Metal-Oxide Device and Method of Manufacturing the Same”,both to be filed concurrently herewith.

TECHNICAL FIELD

The disclosure is directed, in general, to single-electron tunneljunction, and more specifically, to a single-electron tunnel junctionand its method of manufacture in an integrated circuit usingcomplementary metal-oxide semiconductor (“CMOS”) process.

BACKGROUND

A component of a single-electron circuit is a single-electron tunneljunction. Generally, a single-electron tunnel junction has a structuresimilar to a parallel-plate capacitor. In the present Application, theterm “single-electron device” is also commonly used to describe thesingle-electron tunnel junction. In the single-electron tunnel junction,two plates are separated by a dielectric. However, the single-electrontunnel junction has two special properties.

Regarding the first property, the dielectric has to be thin enough toallow for quantum-mechanical tunneling of electrons through thedielectric to occur with an applied electric potential (e.g. around 1Volt). Regarding the second property, the capacitance of the structureshould be small, so small in fact that the addition of a single electroninto the single-electron tunnel junction would result in a significantvoltage change, such as 0.5 volts.

SUMMARY

In one aspect, the disclosure includes a method of manufacturing aparallel redundant array of single-electron devices. The method includes(a) providing a mask for diffusing a plurality of n-doped regionsdefined by a first set of a plurality of active regions, (b) providing amask for disposing a plurality of polysilicon gates defined by a secondset of a plurality of exposed regions, wherein an offset between a firstmember of the plurality of the exposed region of the first set differsin offset from a second member of the plurality of the exposed region ofthe second set, and (c) fabricating the parallel redundant array ofsingle-electron devices as a function of the offset.

Yet another aspect of the disclosure includes a communication device.The communication device includes (a) a radio frequency transceiver, and(b) a single-electron device for use in generating a current referencefor employment with at least one analog circuit of the radio frequencytransceiver.

Yet another aspect of the disclosure includes a device. The deviceincludes (a), a plurality of single-electron devices, and (b) a selectorthat can select a subset of the single-electron devices with anacceptable single-electron effect.

BRIEF DESCRIPTION OF DRAWINGS

The disclosure is described with reference to example embodiments and toaccompanying drawings, wherein:

FIG. 1A illustrates a top view of one embodiment of a single-electrondevice constructed according to the principles of the disclosure;

FIG. 1B illustrates a cross-sectional view of one embodiment of asingle-electron device constructed according to the principles of thedisclosure;

FIG. 2A illustrates a top view of one embodiment of a dualsingle-electron device constructed according to the principles of thedisclosure;

FIG. 2B illustrates a plurality of dual single-electron devicesconstructed according to the principles of the present disclosure;

FIG. 3A illustrates a redundant array of single electron tunnel-junctiondevices constructed according to the principles of the presentdisclosure;

FIGS. 3B and 3C illustrate misalignments of an active mask and apolysilicon mask of FIG. 3A when generating redundant arrays ofsingle-electron devices;

FIG. 4 illustrates a multiplexer circuit for accessing a plurality ofsingle-electron tunnel junction devices constructed according to theprinciples of the present disclosure;

FIG. 5A illustrates a flow chart of one embodiment of a method ofmanufacturing a single-electron tunnel junction in a CMOS carried outaccording to the principles of the disclosure;

FIG. 5B illustrates a flow chart of one embodiment of a method ofmanufacturing a redundant array of single-electron tunnel junctions in aCMOS carried out according to the principles of the disclosure;

FIGS. 6A-6G illustrate cross-section views of selected steps in exampleimplementation of a method of fabricating an single-electron tunneljunction in a CMOS constructed according to the principles of thedisclosure; and

FIG. 7 illustrates simplified block diagram illustrating an examplemobile communication device incorporating the single-electron devicefrequency oscillation and/or generation mechanism of the disclosure.

DETAILED DESCRIPTION

FIG. 1A illustrates a top view of one embodiment of a single-electrondevice 100 constructed according to the principles of the disclosure. Asingle-electron tunnel junction 145 created from a layer of an n-dopedregion 120, an interposing pad oxide (not illustrated) and a polysilicongate 140. In FIG. 1A, the dashed-line around the n-doped area 120 andthe polysilicon gate 140 indicates a desired or drawn geometry, whilethe solid area 120 and 140 indicates the fabricated geometry—aftertaking into account limitations and imperfections in the manufacturingprocess such as lithographic error and over-etching. In this disclosure,“pad oxide” is defined as a dielectric that performs an isolationfunction but with some measurable capacitance, whereas a “field oxide”is defined as a dielectric that substantially provides only an isolationfunction. In one embodiment, the n-doped region 120 is doped witharsenic or phosphorous, and the polysilicon gate is doped with boron.

An overlap area between the n-doped region 120 and the polysilicon gate140, which form two plates of a capacitor-like structure, should besmall, on the order of 5-10 nanometers (nm) by 5-10 nm so that thecapacitance is below, in this example, 1 attoFarad (“aF”). However, sucha design constraint creates problems when trying to manufacturesingle-electron tunnel junctions using standard CMOS fabricationtechniques. Generally, ensuring that a sufficiently small capacitance isrealized in a single-electron tunnel device can be a difficult challengewhen fabricating the single-electron tunnel junction.

For instance, if too large of a capacitance is created, then the voltagechange resulting from the addition of a single-electron to the structuremight not be differentiable from voltage fluctuation due to thermalnoise. One alternative to reduce the capacitance of a parallel platestructure is to arbitrarily increase the thickness of the dielectriclayer. However, this is disallowed in the fabrication a single-electrontunnel junction, as it would inhibit the occurrence of quantummechanical tunneling of electrons, which is desired in thesingle-electron tunnel junction. Although a small structure with a smallcapacitance is desired, reliable fabrication of such structuresstretches the limits of today's MOS and CMOS fabrication processes.

Generally, by making the single tunnel junction 145 sufficiently small,and with an insertion of a suitable pad oxide (to be discussed below)inserted between n-doped region 120 and polysilicon gate 140, acapacitor is formed. By making this area of overlap suitably small, acapacitance is formed whose size is on the same order of magnitude to acharge of a single electron.

FIG. 1B illustrates one embodiment of cross-sectional view of asingle-electron device 100 constructed according to the principles ofthe disclosure. A substrate 155 has disposed thereon the n-doped region120. This cross-sectional view is taken on line 160 on FIG. 1A. In oneembodiment, the substrate 155 is a p-type substrate.

The substrate 155 also has a field oxide 122 disposed on and to a sideof the substrate 155. A pad oxide 123 covers the n-doped region 120 witha thin oxide layer.

The gate polysilicon 140 overlies both the field oxide 122 and anoverhang of the n-doped region 120 with the thin layer of pad oxide 123interposed between. This creates the single-electron tunnel junction145. In other words, the polysilicon gate 140, disposed over part of thethin layer of pad oxide 123, which is disposed over the n-doped region120, forms a capacitance. In some embodiments, a bracing area 180 isused to help support the structure of the polysilicon gate 140. In oneembodiment, the single-electron tunnel junction 145 has about a 5 nm by5 nm area, giving rise to a capacitance of 0.3 attofarads. As a chargeof an electron is approximately 1.6×10⁻¹⁹ coulombs, an addition of asingle electron would result in a voltage change of approximately 0.5volts. For ease of explanation, any stray capacitance of the polysilicongate 140 is assumed negligible. That is an example of acceptablesingle-electron tunnel-junction or, which has good characteristics formeasuring and exploiting single-electron effects. In other embodiments,0.1 volts may be set as a threshold. Single electron devices below thisdiscernable threshold may be deemed unacceptable for single-electroneffects. However, these voltage changes may be generally measurableabove variations in background thermal noise.

In some embodiments, the thickness of the n-doped region 120 is about 90nm. The thickness of the pad oxide 123 is about 1.2 nm. In someembodiments, the capacitance of the single-electron tunnel junction 145is sufficiently small such that the addition of a single electron to thestructure would result in a voltage change that is substantially equalto 1 Volt.

FIG. 2 illustrates one embodiment of top view of a dual single-electrondevice 200 constructed according to the principles of the disclosure. Inthe device 200, n-doped regions 220, 230 are both disposed under apolysilicon gate 240, with a thin layer of pad oxide (not illustrated)disposed in between.

In some embodiments, the polysilicon gate 240 is disposed over a part ofa pad oxide, which is in turn disposed over the n-doped region 230. Thecapacitance of the n-doped region 230 compensates for a deficiency of acapacitance formed by the polysilicon gate 240 disposed over a part ofthe pad oxide disposed, in turn, over the n-doped region 220. In otherwords, if the polysilicon gate 240 is misaligned with respect with itsplacement over the n-doped region 220 such that the capacitance of theresulting single-electron tunnel junction 245 is too large or too small,a second single-electron tunnel junction 247 compensates for it. Byregarding the single-electron tunnel junctions 245, 247 together as aunit having an aggregate capacitance equivalent to the capacitance oftwo single-electron tunnel junctions, the relative placement of thepolysilicon gate 240 to the n-doped region 220 are varied in offset, aswill be described below. In FIG. 2, the n-doped regions 220, 230 arecoupled through metal contacts 250, 255 through a metal connection 257.

Generally, because a desired overlap between an n-doped region and apolysilicon gate is small, precise alignment between the n-doped regionand the polysilicon gate is important. This means the alignment betweena mask for placement of the n-doped region (“active” mask) and apolysilicon mask should be precise. If the active mask and thepolysilicon masks are not precisely aligned, then excess capacitancemight result, or no overlap region would result. For instance, for adesired 5 nm by 5 nm overlap, a standard deviation for mask alignmenterror of 5 nm in a 45 nm gate-length CMOS process generation, results inno gate overlap whatsoever.

Generally, the dual single-electron tunnel device 200 can help alleviatethis problem. Using the dual single-electron device of FIG. 2, if asmall alignment offset exists between the polysilicon gate 240 and then-doped region 220, the aggregate capacitance of both of thesingle-electron tunnel junctions 245, 247 is substantially constant.

Based on the dual single-electron tunnel device 200, the smallestsingle-electron tunnel junction that can be fabricated, with arelatively high yield, can be estimated. In one embodiment, afabrication tool has a worst-case alignment offset of r radially betweenthe n-doped region 220 and a mask for the polysilicon gate 240.Therefore, through use of the dual single-electron device 200, aggregatecapacitance can be made substantially constant for offsets that are nottoo “large,” such as an offset of 5 nm.

For instance, FIG. 2B illustrates various offsets between the n-dopedregion 220, 230 and the polysilicon gate 240. As is illustrated betweenthe first two figures, a deficiency in overlap between the n-dopedregion 220 and the polysilicon gate 240 is compensated for by then-doped region 230.

FIG. 3A generally illustrates one embodiment of a deliberate changing ofoffsets for various single electron tunnel junction devices to generatea parallel redundant array of single-electron tunnel devices havingsingle-electron tunnel junctions 310, 320, 330, 340 constructedaccording to the principles of the disclosure. Generally, in the array300, a plurality of n-doped regions 312, 322, 332, and 342 are placed atdifferent offsets 315, 325, 335, 345 in respect to their respectivepolysilicon gates 314, 324, 334, 344.

Generally, lithography and etching processes to manufacture MOS devices,such as single-electron tunnel junctions, are not completely error-freein the sense that a desired geometry would not appear exactly the sameon a fabricated silicon. This is especially true wherein the minimumfeature sizes of the MOS and CMOS devices are already much smaller thanthe ultra-violet light wavelength used to define them in the lithographyprocess. This creates limitations on a CMOS fabrication system.

One prevalent effect associated with this limitation is that squareedges are rounded. Mask offset is also a problem, along with othervariations in fabrication process. These other variations could be dueto a non-uniform density of an etching solution or due to otherimperfections in a lithography process in a standard CMOS process.Employment of the parallel redundant array 300 could be employed in aplurality of situations in order to improve an overall yield.

Employment of the parallel redundant array 300 could help, first,because a selected dimension of the single-electron tunnel junctionmight be much smaller than a worst-case alignment margin afforded by afabrication tool. In this case, the dual-single-electron device 200 maynot be sufficient to ensure that a sufficiently small overlap area isproduced. Secondly, a random variation in the fabrication process mightalter the geometry of the polysilicon gate and the n-doped region in away not predicted, which again would change the effective overlap area,which would change the capacitance.

In these cases, or in other cases, a parallel redundant structure, suchas the parallel redundant array 300, can be used. In the parallelredundant array 300, as discussed above, several tunnel junctionstructures are drawn in parallel with different overlap (or gap) drawnbetween the n-doped region and the polysilicon gate. This redundancy isperformed in numbers to help guarantee that regardless of themask-shifts, rounding effects, or other random variations, at least oneof the structures results in a selected amount of capacitance. Becausethe individual size of the tunnel junction is small, manufacturing aredundant array of these devices should not take a significant amount ofarea. The redundant array device 300 can provide a high resulting yieldfor the overall system, even if fabrication of individualsingle-electron tunnel junctions might prove to be unreliable.

Generating the redundant array 300 in such a manner can help ensure thatan acceptable single-electron tunnel junction is created somewhere inthe redundant array 300. By deliberately varying the offset between then-doped region and the polysilicon gate in the device layout,misalignment of masks of the polysilicon during the fabrication processcan be rendered less critical, as one of the single-electron devices310, 320, 330, 340 would have an overlap that is closest to a desiredoverlap.

As is illustrated, the different offsets 315, 325, 335, 345 havediffering areas of overlap or distance between their respective n-dopedregions and polysilicon gates, different capacitances are created.Through one-time factory or even power-up testing, it can be determinedwhich of the single-electron tunnel junctions 310, 320, 330, 340 bestmeets capacitance specifications.

FIG. 3B shows the active mask 391 and the polysilicon mask 392 used tofabricate the plurality of single-electron devices 300. The exposed area316, 326, 336, 346 in the active mask 391 defines the resulting printedgeometry of the n-doped region 312, 322, 332, and 342 respectively.Similarly the exposed area 318, 328, 338, 348 in the polysilicon mask392 is used to print the polysilicon structure 314,324,334, and 344respectively. If the two masks 391 and 392 are aligned correctly, thenthe plurality of devices shown in FIG. 3A would result. Note that thegeometry shown in FIG. 3A also includes other fabrication errors such asover-etching, lithography errors etc. In this case the single-electrontunnel-junction 320 has the right amount of capacitance, with the resthaving either too much or too little to no overlap area.

FIG. 3C shows a resulting printed geometry of a polysilicon mask that ismisaligned by a direction and amount indicated by arrow 380 in relationto the placement of the active mask. As seen in FIG. 3C, thesingle-electron tunnel junction 330 instead of 320 has the right amountof overlap area to evince an acceptable single-electron effect.

Although fabrication techniques, through differing offsets, may lead tomanufacturing yields wherein the number of single-electron devices thathave acceptable single-electron effects may be relatively low for agiven manufacturing run, e.g., 20.0%, the present disclosure recognizesthat, through adapting CMOS manufacturing techniques, there is anefficiency in producing a high number of single-electron devices, andthen selecting a subset of those high number single-electron devicesthat evince an acceptable single-electron effect (e.g., voltage changedue to a single-electron that is discernable from thermal noise). Due tothe relatively small chip area or “real estate” that the single-electrondevices occupy, manufactures may generate, through varying offsets, asufficient number of single-electron devices on a given chip.

FIG. 4 illustrates a circuit 400 for selecting from one single electrontunnel junction device from a plurality of the single-electron tunneldevices constructed according to the principles of the presentdisclosure. The single-electron tunnel devices 410, 420, 430 and 440 arecoupled to a multiplexer 450. Each single-electron tunnel device 410through 440 can be selected by a select line. Therefore, a functionalsingle electron tunnel device can be selected. An output of a selectedsingle-electron tunnel device is considered active when selected by themultiplexer 450. Note that the selection could be done by other means,such as selective of the input voltage to each of the single-electrondevices. In that case the multiplexer 450 would not be a physicalmultiplexer as shown in FIG. 4, but a multiplexer mechanism, firmware orsoftware with a variety of approaches to a specific realization of thephysical selection. In some embodiments, each of the single electrondevices has a different internal alignment offset, and is selectable bythe multiplexer 450. The number of the single-electron devices to beselected could be very high, even up to a million or more.

As exemplarily illustrated in single electron device 410, each of theplurality of single-electron circuit 410, 420, 430, 440 include atunneling junction, such as tunneling junction 410, in series with acapacitor 412. In some embodiment, the capacitor 412 is a“non-tunneling” capacitor; in other words, no appreciable tunnelingeffects occur between the anode and the cathode of this capacitor. Thisis only one example of many possible single-electron devices. Thecapacitor 412 can be fabricated by stacking a metal layer on top of thepolysilicon gate 140. This type of structure, such as shown withinsingle-electron device 410, is similar to a “Coulomb blockade”.

FIGS. 5A and 5B illustrates a flow chart of one embodiment of a methodof manufacturing a single-electron tunnel junction in a method 500carried out according to the principles of the disclosure. These will bedescribed in relation to both the FIGS. 6A-6G, and will becross-correlated with the FIG. 1B as appropriate. Generally, method 500is a variation on CMOS fabrication techniques, and the method canadvantageously be used in CMOS fabrication facilities.

In a step 510, a p-type substrate is provided. In one embodiment, thisis a p-type substrate 510 of FIG. 5A. In one embodiment, after etchingand other processing has occurred, the p-type substrate 510 correlatesto the substrate 155 of FIG. 1B.

In a step 515, a pad oxide layer is disposed on the p-type substrate. Inone embodiment, the pad oxide layer is a pad oxide 615 of FIG. 5B, whichis disposed on the p-type substrate 610. In some embodiments, at leastpart of the pad oxide 715 is later to be employed as the pad oxide 123of FIG. 1B.

In a step 520, a nitride layer is disposed on the pad oxide. In oneembodiment, the nitride layer is a nitride layer 720 of FIG. 6B, whichis disposed on the pad oxide 715.

In a step 525, a nitride window is formed in the nitride layer. In oneembodiment, the nitride windows are nitride windows 830, 832 of FIG. 6C.In one embodiment, the nitride window 730 and 732 is created by using acombination of photolithography and etching, as may be used in astandard CMOS process. As is illustrated, the etching process onlyremoves a part of the nitride layer, as defined by a photolithographymask. The etching process in the step 525 does not remove the pad oxide715.

In a step 530, a field oxide is disposed in the nitride window. In oneembodiment, the field oxide is a field oxide 945 of FIG. 5D. The padoxide 715 and the field oxide 945 have the same chemical composition,which is silicon dioxide. Once a nitride window is formed, the chip“die”, containing the pad oxide 715 and the field oxide 945 is thenheated, such as being placed in a furnace. Any area of the chip “die”that is not covered by the nitride layer 720 undergoes furtheroxidation. This oxidation process then ‘grows’ or expand the pad oxidelayer 715 above and below the existing pad oxide 715. When undergoingthe oxidation process, the nitride layer also gets very slowly oxidized,but occurs at a much slower rate than the oxidation process in exposedsilicon/silicon dioxide of the chip. In some embodiments, the nitridelayer 720 after this step is slightly “rounded.”

In a step 535, the nitride layer is removed. In one embodiment, thenitride layer 520 is illustrated as removed in a FIG. 5E.

In a step 540, a polysilicon gate is disposed over the field oxide. Thepolysilicon gate is defined through a photolithography process with aseparate masking layer. In one embodiment, the polysilicon gate is apolysilicon gate 1050 of FIG. 6F. In one embodiment, the polysilicongate 1050 correlates to the polysilicon gate 240 of FIG. 2A.

In a step 545, an n-doped region is implanted in the p-type substrate,thereby forming at least one single-electron tunnel junction between thepolysilicon gate and the n-doped regions. The area for implantation isalso defined through a photolithography process with a separate masklayer. In one embodiment, the n-doped regions are the n-doped regions1160 and 1162 of FIG. 6G. This diffusion of n-doped regions createssingle-electron tunnel junctions 1165, 1167 between the n-doped regions1160, 1162, and the polysilicon gate 1050, respectively. In oneembodiment, after method 500, the n-doped regions 1160, 1162 correspondto the n-doped region 220 and 230 of FIG. 2A.

In one embodiment, the field oxide is provided to a side of the p-typesubstrate. The n-doped region is diffused beneath the polysilicon gateto form a single tunnel junction. A first and second tunnel junction isformed at a first and second end, respectively, of the polysilicon gate.

In one embodiment of the method 500, a first mask is provided for usewith diffusing the n-doped region in the p-type substrate. A second maskis provided for use with disposing the polysilicon gate. A first andsecond single-electron tunnel junction is employed to help alleviate amask-alignment mismatch between the first mask and the second mask.

FIG. 5B illustrates a flow chart of one embodiment of a method 550 ofmanufacturing a redundant array of single-electron tunnel junctions in aMOS or CMOS practiced according to the principles of the disclosure.

In a step 560, a mask is provide for diffusing a plurality of n-dopedregions defined by a first set of a plurality of exposed regions of amask.

In a step 570, a mask is provided for disposing a plurality of n-dopedactive areas defined by a plurality of exposed areas is staggered inlength. In other words, the lengths of the exposed areas of the mask areof differing lengths.

In a step 580, a parallel redundant array of single-electron devices aremanufactured as a function of the offsetting, such as illustrated in themethod of FIG. 5A.

FIG. 7 illustrates a simplified block diagram illustrating an examplecommunication device 870 incorporating the single-electron device andsingle-electron oscillator constructed according to the principles ofthe present invention. The communication device may comprise anysuitable wired or wireless device such as a multimedia player, mobilestation, mobile device, cellular phone, PDA, wireless personal areanetwork (WPAN) device, Bluetooth EDR device, etc. For illustrationpurposes only, the communication device is shown as a cellular phone orsmart phone. Note that this example is not intended to limit the scopeof the invention as the SED mechanism of the present invention can beimplemented in a wide variety of wireless and wired communicationdevices.

The cellular phone, generally referenced 870, comprises a basebandprocessor or CPU 871 having analog and digital portions. The basiccellular link is provided by the RF transceiver 894 and related one ormore antennas 896, 898. A plurality of antennas is used to provideantenna diversity which yields improved radio performance. The cellphone also comprises internal RAM and ROM memory 910, Flash memory 912and external memory 914.

In accordance with one aspect of the present disclosure, a singleelectron device 928 is employed by the RF transceiver 894. The singleelectron device 928 could be either internal or external to the RFtransceiver 894. In some embodiments, the radio frequency deviceincludes a plurality of single electron devices in an array, such asdescribed in FIG. 3A, or can be dual single electron devices, such as inFIG. 2A.

Generally, the single-electron devices could be used for generation oflocal oscillator clocks. The single electron device could also be usedto generate a stable bias current reference or voltage reference forvarious analog and RF circuits that comprise the radio. The current canbe accurately generated by exploiting the single-electron characteristicof a Coulomb blockade in which a single-electron (i.e., charge) transferis virtually guaranteed beyond a certain time interval, which istypically on the order of tens of picoseconds. Moving a fixed charge “e”within a well-controlled period “T” of a clock in a repetitive mannerwill give rise to a well-controlled current I=e/T, which could be usedin as a low-noise reference current for analog and RF circuits. Toincrease this current, multiple single electron devices could be used.An output of the plurality of the single-electron devices is controlledto be active or inactive, such as by the multiplexer 450 of FIG. 4.

Several user interface devices include microphone 884, speaker 882 andassociated audio codec 880, a keypad for entering dialing digits 886, avibrator 888 for alerting a user, camera and related circuitry 900, a TVtuner 902 and associated antenna 104, display 106 and associated displaycontroller 908 and GPS receiver 890 and associated antenna 892.

A USB interface connection 878 provides a serial link to a user's PC orother device. An FM receiver 872 and antenna 874 provide the user theability to listen to FM broadcasts. WLAN radio and interface 876 andantenna 877 provide wireless connectivity when in a hot spot or withinthe range of an ad hoc, infrastructure or mesh based wireless LANnetwork. A Bluetooth EDR radio and interface 873 and antenna 875 provideBluetooth wireless connectivity when within the range of a Bluetoothwireless network. Further, the communication device 870 may alsocomprise a WiMAX radio and interface 923 and antenna 925. SIM card 916provides the interface to a user's SIM card for storing user data suchas address book entries, etc. The communication device 870 alsocomprises an Ultra Wideband (UWB) radio and interface 883 and antenna881. The UWB radio typically comprises an MBOA-UWB based radio.

Portable power is provided by the battery 924 coupled to batterymanagement circuitry 922. External power is provided via USB power 918or an AC/DC adapter 920 connected to the battery management circuitrywhich is operative to manage the charging and discharging of the battery924.

Those skilled in the art to which the disclosure relates will appreciatethat other and further additions, deletions, substitutions, andmodifications may be made to the described example embodiments, withoutdeparting from the disclosure.

1. A method of manufacturing a parallel redundant array ofsingle-electron devices, comprising: providing a mask for diffusing aplurality of n-doped regions defined by a first set of a plurality ofactive regions; providing a mask for disposing a plurality ofpolysilicon gates defined by a second set of a plurality of exposedregions, wherein an offset between a first member of the plurality ofthe exposed region of the first set differs in offset from a secondmember of the plurality of the exposed region of the second set; andfabricating said parallel redundant array of single-electron devices asa function of said offset.
 2. The method of claim 1 wherein at least twosingle-electron devices of the parallel redundant array ofsingle-electron devices have a differing capacitance from one another asa function of the offsetting of the at least two of the plurality ofmasks.
 3. The method of claim 1, wherein a capacitance of at least onesingle-electron device of the parallel redundant array ofsingle-electron devices can store only a single electron.
 4. The methodof claim 1, further comprising employing at least one single-electrondevice of said single-electron devices as an oscillator.
 5. The methodof claim 1, further comprising selecting at least one of saidsingle-electron devices that has an acceptable single-electron effect.6. The method of claim 5, wherein said acceptable single electron effectis a voltage change of 0.1 Volts associated with said single-electrondevice.
 7. The method of claim 5, wherein said acceptable singleelectron effect is a voltage change associated with a single-electrondevice that is discernable from thermal noise.
 8. The method of claim 5,wherein said single single-electron device generates a bias referencecurrent.
 9. A communication device, comprising: a radio frequencytransceiver; and a single electron device for use in generating acurrent reference for employment with at least one analog circuit ofsaid radio frequency transceiver.
 10. The communication device of claim9, further comprising a plurality of single electron devices.
 11. Thecommunication device of claim 10, wherein an output of said plurality ofsaid single-electron devices is controlled to be active or inactive. 12.The communication device of claim 9, wherein said communication deviceis a cellular phone.
 13. The communication device of claim 9, wherein acapacitance of said single-electron device can store only a singleelectron.
 14. A device, comprising: a plurality of single electrondevices, a selector that selects a subset of said single electrondevices that have an acceptable single-electron effect.
 15. The deviceof claim 14, wherein said acceptable single-electron effect is a voltagechange associated with a single-electron device that is greater than 0.1Volts.
 16. The device of claim 14, wherein said acceptable singleelectron effect is a voltage change associated with a single-electrondevice that is discernable from thermal noise.
 17. The device of claim14, wherein at least two of said plurality of said single-electrondevices have a different internal alignment offset.
 18. The device ofclaim 14, wherein at least one single-electron device of said pluralityof single-electron devices has an associated single-electron effectacceptable, and at least one single-electron device of said plurality ofsingle-electron devices has an associated single electron effect that isnot acceptable; and wherein said selector, coupled to said plurality ofsingle-electron devices, selects said at least one single-electrondevice having said acceptable single-electron effect.
 19. The device ofclaim 14, wherein no more than 20% of said single-electron devices haveacceptable single-electron characteristics.
 20. The device of claim 14,wherein a subset is a single single-electron device.
 21. The device ofclaim 14, wherein a capacitance of at least one single-electron deviceof the parallel redundant array of single-electron devices can storeonly a single electron.
 22. The device of claim 14, wherein saidselector is a multiplexer.